1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and, more particularly, to a semiconductor integrated circuit having a voltage level conversion circuit and at least two types of logic circuit elements that operate at power supply voltages having different values.
2. Description of the Related Art
With the trend toward smaller semiconductor integrated circuits, in order to ensure the reliability of internal circuit elements and reduce the power consumption it is preferable to decrease the supply voltage. At a low supply voltage, however, an internal circuit cannot be operated at a high speed or a write cannot be sufficiently done in memory cells. The above requirements for reliability and low power consumption can be achieved by applying a high power supply voltage to a necessary portion of a semiconductor integrated circuit and operating it.
Since power supply voltages having different values are applied to a single semiconductor integrated circuit, and circuits designed to perform logic processing at different signal levels are mounted together, a level conversion circuit for converting signal levels is required between the two circuits.
In a conventional semiconductor integrated circuit including a level conversion circuit, an output signal from a logic circuit to which a lower power supply voltage is applied is input to the level conversion circuit to which two types of power supply voltages, i.e., higher and lower voltages, are applied, the level conversion circuit converts the amplitude of the output signal having a level corresponding to the lower power supply voltage to the amplitude corresponding to the higher power supply voltage, and the resultant voltage signal is output to the circuit that operates at the higher power supply voltage (see, for example, U.S. Pat. No. 6,067,257 (Page 1, FIG. 7)
With the recent trends toward mobile electronic devices, a specified voltage may not always be applied to such a semiconductor integrated circuit having different power supply voltage levels when a power supply voltage is applied from a battery exhausted upon discharging or from a charging power supply or a shock, vibration, or the like is given to a power supply circuit including a battery. More specifically, when the higher power supply voltage becomes unstable, the voltage will be lowered to a value lower than that of the lower power supply voltage. Alternatively, the connection terminal of the lower voltage supply may undergo unstable contact, and the power supply may be instantaneously interrupted or stopped.
A fluctuant power supply voltage lower than the minimum level required to determine a logical operation may therefore be applied to a logic circuit element. As a consequence, the logic operation of the logic circuit element becomes unstable. In this case, for example, the conduction state of transistors forming an inverter formed of a CMOS circuit may become unstable, and a leakage current may flow across the power supply terminals of this inverter via the CMOS circuit. As described above, leakage current may flow in various portions of a semiconductor integrated circuit due to unstable power supply voltages, and hence operation errors and increases in power consumption have not been prevented.
A conventional semiconductor integrated circuit including a level conversion circuit will be described below with reference to FIGS. 8A and 8B. FIG. 8A shows a block diagram of a semiconductor integrated circuit having a level conversion circuit 83 between a logic circuit 81 to which a power supply voltage VL is applied and a logic circuit 82 to which a power supply voltage VH is applied. The power supply voltage VH is higher than the power supply voltage VL.
This semiconductor integrated circuit includes the logic circuit 81 to which the power supply voltage VL is applied and which outputs a signal S1 having the amplitude corresponding to the power supply voltage VL, the level conversion circuit 83 which is connected to the logic circuit 81, to which the power supply voltages VL and VH are applied, and which converts the input signal S1 into a signal S2 having the amplitude corresponding to the power supply voltage VH and outputs the signal S2, and the logic circuit 82 to which the power supply voltage VH is applied and which outputs a signal S3 having the amplitude corresponding to the power supply voltage VH. A simple logic element (to be referred to as an H•L conversion logic element hereinafter) such as an inverter, NAND circuit, or NOR circuit (not shown) for level-converting the signal S3 into a signal having the amplitude corresponding to the power supply voltage VL is further connected to the input stage of the logic circuit 81.
Assume that in this case, the logic circuits 81 and 82 include CMOS inverters which are constituted by PMOS and NMOS transistors and receive input signals at their commonly connected gates.
FIG. 8B is a circuit diagram showing an example of the level conversion circuit 83. The level conversion circuit 83 includes a latch circuit. This latch circuit is comprised of PMOS transistors P84 and P85 having source terminals to which the power supply voltage VH is applied and gate terminals and drain terminals which are cross-connected to each other, an NMOS transistor N84 having a drain terminal connected to ground and a source terminal connected to the drain terminal of the PMOS transistor P84 and the gate terminal of the PMOS transistor P85 at a node 86, and an NMOS transistor N85 having a drain terminal connected to ground and a source terminal connected to the drain terminal of the PMOS transistor P85 and the gate terminal of the PMOS transistor P84 at a node 87.
The level conversion circuit 83 is further comprised of an inverter 88 to which the power supply voltage VL is applied and which has an output terminal to which the gate terminal of the NMOS transistor N84 and the input terminal of an inverter 89 are connected and outputs the signal obtained by inverting the logic of the input signal S1, the inverter 89 which outputs the signal obtained by inverting an input signal from the inverter 88 to the gate terminal of the NMOS transistor N85, and an inverter 810 to which the power supply voltage VH is applied and which outputs the signal S2 obtained by inverting the logic of an input signal from the node 87.
The operation of the semiconductor integrated circuit including the level conversion circuit 83 shown in FIGS. 8A and 8B will be described next.
Conversion (to be referred to as L•H conversion hereinafter) from the signal S1 having the amplitude corresponding to the power supply voltage VL to the signal S2 having the amplitude corresponding to the power supply voltage VH will be described first with reference to FIG. 8B. When the signal S1 having high level (to be referred to as logic-H hereinafter) of the power supply voltage VL is input to the level conversion circuit 83, the logic-H signal S1 is inverted into a signal having low level (to be referred to as logic-L hereinafter) by the inverter 88. This signal is output to the NMOS transistor N84 and inverter 89. The logic-L signal input to the gate terminal of the NMOS transistor N84 turns off the NMOS transistor N84.
The logic-L signal input to the inverter 89 is inverted into a logic-H signal having the amplitude VL. This signal is input to the gate terminal of the NMOS transistor N85 to turn on the NMOS transistor N85. The potential of the node 87 is then pulled down to low level to turn on the PMOS transistor P84 having the gate terminal to which the potential of the node 87 is input. The potential of the node 86 is set at high level to turn off the PMOS transistor P85 having the gate terminal to which the potential of the node 86 is input. Therefore, the logic-L signal is input to the inverter 810 having an input terminal to which the node 87 is connected, and the inverter 810 outputs an inverted high level signal having the amplitude corresponding to the power supply voltage VH.
When the logic-L signal S1 having the amplitude corresponding to the power supply voltage VL is input to the level conversion circuit 83, the logic-L signal S1 is inverted into a logic-H signal by the inverter 88. This signal is output to the NMOS transistor N84 and inverter 89. The logic-H signal input to the gate terminal of the NMOS transistor N84 turns on the NMOS transistor N84. On the other hand, the logic-H signal input to the inverter 89 is inverted into a logic-L signal. This signal is input to the gate terminal of the NMOS transistor N85 to turn off the NMOS transistor N85.
The potential of the node 87 is then set at high level to turn off the PMOS transistor P84 having the gate to which the potential of the node 87 is input. The potential of the node 86 is pulled down to low level to turn on the PMOS transistor P85 having the gate to which the potential of the node 86 is input. Therefore, a high-level signal is input to the inverter 810 having an input terminal connected to the node 87, and the inverter 810 outputs the low-level signal S2 having the same amplitude as that of the power supply voltage VH.
H-L conversion from the amplitude corresponding to the power supply voltage VH to the amplitude corresponding to the power supply voltage VL will be described. The power supply voltage VH is higher than the power supply voltage VL, and the amplitude corresponding to the voltage of a signal input to the logic circuit 81 which operates with the low voltage VL is sufficiently large. Since sufficient signal level is ensured in the logic circuit 81 by this input signal, no latch circuit for fixing logic is required. Therefore, the H•L conversion logic element connected to the first stage of the logic circuit 81 is sufficient in terms of operation, accurate logic operation can be expected without using a level conversion circuit like the circuit 83 shown in FIG. 8B as long as the power supply voltages VL and VH are normal.
Operation to be performed when the power supply voltage VH is unstable, and temporarily becomes lower than the power supply voltage VL will be described. In the level conversion circuit 83, the signal S1 from the logic circuit 81 to which the power supply voltage VL is applied is input to the inverter 88, and hence the signal S1 having the amplitude corresponding to the power supply voltage VL having normal logic level is input. However, since the power supply voltage VH applied to the latch circuit 83 is unstable, the potential of the node 87 to which the unstable power supply voltage VH is applied is also unstable. As a consequence, a logic-undefined signal is supplied to the inverter 810 having the input terminal connected to the node 87. With this operation, a leakage current may flow in the inverter 810 constituted by a CMOS circuit. In addition, since the power supply voltage VH applied to the inverter 810 is unstable, the potential state of the output signal S2 becomes unstable, and the logic-undefined signal S2 may be output.
This logic-undefined signal S2 is input to the logic circuit 82. For this reason, a leakage current may flow in the CMOS inverter and the like in the logic circuit 82. In addition, since the unstable power supply voltage VH is applied, the potential state of an output signal becomes unstable, and the logic-undefined signal S3 is output.
This logic-undefined signal S3 is input to the H•L conversion logic element (not shown) connected to the first stage of the logic circuit 81. If, for example, this logic element is a CMOS inverter, since the logic-undefined signal S3 is input, a leakage current may flow. In addition, the logic-undefined signal S3 is output to the logic circuit 81, and a leakage current also may flow in the logic circuit 81.
As described above, a leakage current flows in the level conversion circuit 83, logic circuit 82, the H•L conversion logic element, and logic circuit 81, resulting in an increase in the power consumption of the overall semiconductor integrated circuit.
Operation to be performed when the lower power supply voltage VL is unstable and instantaneously interrupted or stopped will be described. In this case, since the unstable power supply voltage VL is applied to the logic circuit 81, the logic-undefined signal S1 is output. This logic-undefined signal S1 is input to the level conversion circuit 83. Since this logic-undefined signal S1 is input, a leakage current flows in the inverter 88. Since the unstable power supply voltage VL is applied to the logic circuit 81, a logic-undefined signal is output. This logic-undefined signal is input to the gate terminal of the NMOS transistor N84. As a consequence, the conduction state of the NMOS transistor N84 becomes unstable.
Since the unstable power supply voltage VL is also applied to the inverter 89 in the same manner, a logic-undefined signal is output. This logic-undefined signal is input to the gate terminal of the NMOS transistor N85, and the conduction state of the NMOS transistor N85 becomes unstable. That is, the relationship in conduction state between the NMOS transistors N84 and N85 becomes unstable, and hence the two transistors may be simultaneously turned on. As a result, the node 86 or 87 is set in a low state, and both the PMOS transistors P84 and P85 may be turned on at once. Therefore, a leakage current flows in the latch circuit. In addition, since the logic-undefined signal can be input to the inverter 810, a leakage current flows, and the logic-undefined signal S2 is output.
Since this logic-undefined signal S2 is input to the logic circuit 82, a leakage current flows in the logic circuit 82, and the logic-undefined signal S3 is output.
Furthermore, a leakage current also flows in the simple logic element which is connected to the first stage of the logic circuit 81 and to which the power supply voltage VL is applied, and a logic-undefined signal is output. As a consequence, a leakage current also flows in the logic circuit 81.
The power consumption due to a leakage current generated by an element to which the higher power supply voltage VH is applied as an operating voltage, in particular, increases.
As described above, owing to the possibility that a leakage current will be generated by a semiconductor integrated circuit, a leakage current undesirably flows in the overall circuit although a circuit designed for a mobile device should be a low-power-consumption circuit.